Verification Engineer

Publiceringsdatum: 2025-09-19

Letar du efter anställning inom data/it? Här är din möjlighet att bli en del av teamet hos Arm Sweden AB genom att arbeta som civilingenjör, systemutveckling. Arm Sweden AB söker en medarbetare på heltid som vill arbeta tills vidare. Kan det vara du?

Om du redan bor i närheten av Lund, är det här din chans att söka ett spännande jobb Arm Sweden AB söker för närvarande efter en person att anställa inom civilingenjör, systemutveckling-branschen. Ta en titt på deras lediga tjänst för att se om något av dem passar just dig. Sök jobbet som civilingenjör, systemutveckling hos Arm Sweden AB och ta chansen att ta din karriär till nästa nivå. Ansök senast fredag den trettioförsta oktober 2025.

Jobbannons

We’re looking for a highly qualified SV UVM Verification Engineer who brings deep expertise in SystemVerilog/UVM-based verification along with a solid formal verification background. This role is ideal for someone who thrives in hands-on verification, enjoys working across simulation and formal domains, and is passionate about driving quality and efficiency in complex IP development.

Collaborating with experts across global design centers, you’ll drive impactful projects and help deliver Arm’s next-generation IP using the most sophisticated tools and methodologies.

Job Description:

GPU HW Team in Lund (Sweden), has an extraordinary opportunity for a highly motivated and experienced Verification Engineer to join our expanding GPU HW team and embark on the development journey of one of the world's most sophisticated GPU designs.

You will be acting as a key verification stakeholder in our HW development team. You will be involved in developing formal test benches by deploying formal properties verification techniques to ensure our modules are verified according to the top-notch industry standards. You are comfortable and confident taking ownership of complex work packages and driving them to closure and success.

Responsibilities:

As an Experienced Verification Engineer, you'll be responsible for shaping and executing robust IP verification strategies. Your role will focus both on traditional simulation-based techniques and formal verification methods, ensuring high standards are met throughout the entire development lifecycle.

• Full ownership and execution of IP verification work package from the test planning phase to project closure.
• 10+ years of SystemVerilog/UVM experience to develop, maintain, and evolve scalable verification environments.
• Good understanding of functional verification principles, strategies and techniques.
• Collaborate closely with design, verification and formal team to ensure robust testbench architecture and coverage closure.
• Proficient user of version control, test management and issue tracking tools.
• Monitor and improve verification performance using collected metrics and data-driven techniques.

Required Skills and Experience:

• 10+ years of industry experience in IP/block-level verification using SystemVerilog and UVM.
• Formal property verification knowledge and expertise. Proficiency with formal verification tools (e.g., Cadence Jasper-Gold, Synopsys VC Formal, or equivalent).
• Good interpersonal skills and ability to efficiently work as part of a highly collaborative team.
• Results oriented with a proactive mindset and a strong drive for continuous improvement.

“Nice To Have” Skills and Experience:

• Knowledge of graphics principles.
• Experience with scripting (Python, Linux shell) to automate and optimize verification workflows.
• Skilled in planning verification tasks and producing realistic effort and time estimates.
• Exposure to Functional Safety (ISO 26262) and Cybersecurity (ISO 21434) verification practices.